MOS transconductance amplifier for active filters

ABSTRACT

A differential input, differential output transconductor for IC fabrication comprises a matched pair of field-effect transistors (10) whose source terminals (11) are connected together to a first fixed voltage, the substrate terminals are connected together to a second fixed voltage and the quiescent voltages of the gate terminals (12) are equal. The FETs are biassed in the triode region of operation for the expected gate-source voltage and signal voltages of equal but opposite polarity are superimposed on the gate terminals (12) of the FETs. Circuitry is disclosed to maintain the voltage of the drain terminals (13) and to transmit the differential - mode output current component at a higher impedance level to output circuitry. A common-mode bias stabilization circuit, a phase neutralizing circuit and active filter circuits are also disclosed.

IMPROVEMENTS IN OR RELATING TO TRANSCONDUCTORS

The present invention relates to transconductance amplifier stagesemploying field effect transistors and particularly though notexclusively to active filters including MOST transconductance stages andcapacitors, fabricated as monolithic integrated circuits.

Conventional types of RC active filter have the potential to beconstructed using integrated circuits technology. This requires that thetime constants or RC products of these circuits must be accuratelydefined, implying that the absolute values of resistance and capacitanceshould be closely controllable. This is not possible however with themanufacturing tolerances and temperature coefficients typicallyassociated with monolithically integrated components.

Switched capacitor circuits offer one solution to this problem. Thesegive a frequency domain transfer function with shape defined by ratiosof capacitors and with the frequency axis scaled by an accurateexternally generated clock frequency. However such filters are sampleddata in nature and so in general require an anti-aliasing prefilter anda smoothing post-filter to interface satisfactorily with continuous timeor asynchronously sampled circuitry. High frequency components of powersupply noise and operational amplifier noise can be coupled into thesignal path and aliased into the baseband filter output. The multi-phasenon-overlapping clock waveforms generally necessary require carefullydesigned clock generators and buffers. The high frequency components ofthese waveforms can radiate to interfere with other circuitry. Thesynthesis of such filters requires special techniques and specialpurpose circuit simulators.

An alternative circuit concept involves the use of integratedtransconductance amplifiers or "transconductors". In combination withon-chip capacitors in appropriate circuit topologies, these have thepotential to realise filters with a wide range of frequency responses.The time-constants of such circuitry are defined by the values oftransconductance and capacitance. The shape of the frequency response isdetermined by the ratios of capacitors and by the ratios oftransconductances and is thus insensitive to correlated manufacturingvariability in the absolute values or to uniform temperature variations.The frequency axis is scaled according to the absolute values of thetransconductances and capacitances and so will vary widely withmanufacturing tolerances and temperature variations. This variation canbe removed however by using a known "master-slave" approach. In this,the transconductance of all the transconductors is controlled to beequal to that of an extra identical transconductor, which is part of acontrol loop such as a phase-locked loop locked onto an externalreference frequency or a feedback loop based on an external referenceresistor.

Several such circuits are known, using bipolar technology. However, MOStechnology and CMOS in particular has general advantages of a higherpacking density, operation at lower current densities, and highercircuit impedances, leading to compact and low-power circuitry. Digitalcircuitry can also be readily included on the same chip. Theseconsiderations have led to improved circuits for MOS transconductors,particularly in CMOS, though the invention is also thought to beapplicable to other similar technologies, including but not exclusivelysingle channel MOS, JFET or MESFETS.

MOS long-tailed pair circuits have been suggested for use astransconductance stages, but even when extra circuitry is added thesesuffer from limited signal range and non-linear distortion, particularlywhen the variations of bias point with manufacturing tolerances andtemperature are taken into account. Fullydifferential circuitry using apair of common-source MOSTs, biased to operate in the saturation regionof operation, has been suggested, but the transconductance is thendependent on common mode input signals and even a differential inputsignal component gives rise to a large common-mode output current,placing stringent requirements on the common-mode performance of thecircuitry. The use of MOSTs in the triode region to act asvoltage-controlled resistors has been suggested, but again theresistance is strongly dependent on common-mode signal voltage.

One aim of the present invention is to provide a differential-inputdifferential-output transconductance stage with low distortion andadequate signal swing, low common-mode output current and with atransconductance set by an external control terminal but independent ofcommon-mode signal voltages. This transconductor can then be used withcapacitors connected in appropriate networks such as described below toimplement a filter. It could also be used in other known circuitconfigurations.

The invention comprises a differential input transconductor including apair of field-effect transistors, wherein:

the source terminals are connected together to a fixed voltage, thesubstrate terminals are also connected together, to a second fixedvoltage, possibly but not necessarily to the same voltage as the sourceterminals,

the quiescent voltages of the gate terminals are equal and signalvoltages of equal amplitude but opposite polarity are superimposed onthese terminals,

and the drain voltages of the two FETs are equal and are set at anappropriate voltage to keep the transistors in the triode region ofoperation for the expected variation of gate source voltage.

As shown below, the output currents flowing though the drain terminalswill comprise a common-mode component, largely independent of inputsignal voltage and a differential component proportional to the inputsignal and with magnitude also controlled by the drain-source voltage,but largely independent of the input common-mode voltage.

In the design of a useful transconductance stage, extra circuitry is ingeneral necessary to maintain the drain terminals at constant voltageand to transmit the differential-mode output current component at ahigher impedance level to the load circuitry. This additional outputcircuitry can be a common-gate MOS stage or a common-base bipolartransistor. For minimum distortion, however, more complex circuitry isnecessary as described below.

Practical circuits also require common-mode bias stabilisation, andcircuits to perform this function have been devised. A suitable controlloop circuit has also been derived to stabilise the transconductancewith respect to an external resistor to compensate for the effects oftemperature and manufacturing tolerances on the transconductance of thetransconductor.

For best performance the transistors should be well-matched in geometryand electrical parameters, but the invention is tolerant of small devicemismatches.

Transconductors in accordance with the invention can be incorporatedinto a network of capacitors to realise filters and various examples ofsuch filters are described below. Simple circuit topologies have beendesigned to implement equivalents of LC ladder filters, both all-poleand with transmission zeros. Variants of these filters use eitherfloating or grounded capacitors, and implement transmission zeros eitherwith floating capacitors or through pairs of capacitors connected tolow-impedance nodes.

The invention will now be described by way of example only withreference to accompanying drawings of which:

FIG. 1 is a circuit diagram illustrating the current-voltagerelationships for an N channel MOST;

FIG. 2 shows a fully differential transconductor circuit having two Nchannel MOSTs to illustrate the present invention;

FIGS. 3 and 4 show half-circuit modifications to FIG. 2 to maintain thedrain-source voltage difference of the MOSTs;

FIG. 5 shows a further modification to the half-circuit of FIG. 4;

FIGS. 6a and 6b shows a schematic representation and a detailed circuitdiagram of a transconductor using discrete components;

FIG. 7 shows in detail the common mode (CM) bias stage of FIG. 6b;

FIG. 8 is a block diagram of a voltage controlled current source circuitusing a transconductor;

FIG. 9 is a graph of the variation of 3rd harmonic distortion withoutput signal level for the FIG. 8 circuit;

FIG. 10 is a block diagram of a gyrator including two transconductors;

FIG. 11 shows a conventional LC ladder prototype for a 3rd order 0.1 dBChebyshev filter circuit;

FIG. 12 shows the circuit of FIG. 7 with the inductors replaced bygyrators and grounded capacitors;

FIG. 13 shows the FIG. 12 circuit with the gyrators replaced bytransconductors;

FIG. 14 shows the Chebyshev filter using transconductors;

FIGS. 15a and 15b are graphs of the measured frequency response of theFIG. 14 filter;

FIG. 16 shows graphs illustrating the frequency variation of theharmonic distortion of the FIG. 14 filter;

FIG. 17 shows the harmonic distortion against signal amplitude at 850 Hzfor the FIG. 14 filter;

FIG. 18 shows an LC prototype circuit which is a modification of theFIG. 11 prototype;

FIG. 19 shows a transconductor circuit derived from the FIG. 18prototype;

FIG. 20 shows a modification of the FIG. 19 circuit to reduce the effectof parasitic capacitances;

FIG. 21 is a form of current amplifier suitable for use in the FIG. 20circuit;

FIG. 22 shows a modification of the FIG. 5 transconductor half-circuitincorporating the current amplifier function of FIG. 20;

FIG. 23 shows an elliptic filter derived from the FIG. 14 Chebyshevfilter;

FIG. 24 is a graph of the measured frequency response of the 3rd orderLP filter shown in FIG. 23;

FIG. 25 shows graphs illustrating the frequency variation of theharmonic distortion of the FIG. 23 filter;

FIG. 26A is a shematic view showing a part of FIG. 26;

FIG. 26 shows a transconductor fabricated from MOSTs;

FIG. 27 shows the simulated output harmonic variation of the FIG. 26transconductor;

FIG. 28 shows a modified transconductor having additional signal inputconnectors;

FIG. 29 shows a further modified transconductor having a single sidedoutput;

FIG. 30 illustrates a transconductance stabilisation circuit using theFIG. 29 transconductor;

FIG. 31 shows a 5th order elliptic filter using transconductors shown inFIGS. 26, 28 and 29;

FIG. 32 shows graphs of the frequency response of the FIG. 31 filter,with and without phase neutralisation;

FIG. 33 shows the frequency response of the FIG. 31 filter aftertolerancing for process and temperature extremes;

FIG. 34 shows the FIG. 32 responses after tolerancing;

FIG. 35 shows an alternative transconductor filter arrangement, and

FIGS. 36 to 39 show performance graphs obtained using a filter circuitbroadly as shown in FIG. 35.

The basic principle behind the invention will now be explained withreference to FIG. 1, illustrating an N channel MOST. Reference numerals11-13 refer respectively to the source, gate and drain of a MOST 10. Theusual first-order equation for the drain current of an MOS transistorbiased in its triode region of operation is

    Ids=k' (W/L) [Vgs-Vt)-Vds/2]Vds                            (1)

where:

Ids is the current flowing into the drain terminal;

k' is a process-dependent constant;

W is the transistor width;

L is the transistor length;

Vgs is the applied gate-source voltage;

Vt is the gate threshold voltage; and

Vds is the applied drain source voltage.

This equation is valid for Vgs>Vds+Vt. If Vds is held constant while Vgsis increased from a quiescent value of Vgso to (Vgso+ΔVgs), a change indrain current is predicted, from the quiescent value Idso to (Idso+ΔIds)where the incremental increase ΔIds is given by:

    ΔIds=k' (W/L)VdsΔVgs                           (2)

This implies a perfectly linear transconductance G given by:

    G=k' (W/L)Vds                                              (3)

From observations of actual device characteristics however, k' is foundto vary significantly with Vgs. A commonly-used empirical approximationof this dependence is given by:

    k'=ko'/[1+θ(Vgs-Vt)]                                 (4)

with θ typically between 0.03 and 0.20 per volt, the value of θ varyingwith process details and device geometry. The effect is usually ascribedto mobility degradation due to increased electric field normal to thechannel. This variation in k' with Vgs causes a similarly largevariation in the observed transconductance, as is shown by the followinganalysis.

Substituting for k' in eqn (1) from eqn (4), and letting Vgs=Vgso+ΔVgsand Ids=Idso+ΔIds, we obtain: ##EQU1##

Further, substituting ##EQU2## this equation may be re-written ##EQU3##

For typical values of θ'=0.1 and ΔVgs=1V, this gives a 10% degration inlarge signal transconductance G=ΔIds/ΔVgs. This is an unacceptablenon-linearity for most applications.

The key to reducing this non-linearity is the adoption of a fullydifferential circuit as shown in FIG. 2, comprising a pair of identicalMOS transistors, having the same reference numerals as in FIG. 1. Thesources 11 are connected together to a fixed voltage 14 (taken as groundin this analysis) with their substrate terminals also connected togetherto a fixed voltage (also taken as ground in this analysis). The voltagesat the drains 13 are maintained at equal and constant voltage by extracircuitry (not shown for the sake of simplicity), and the input signalΔVgs is shared equally between the two gates 12.

Defining the drain current of transistor 1 as Ids1=Idso+ΔIds1 and thedrain current of transistor 2 as Ids2=Idso+ΔIds2, and following asimilar analysis to that resulting in eqn (13): ##EQU4##

So the differential output current ΔIds=ΔIds1-ΔIds2 is given by ##EQU5##

Taking ΔVgs=1V and θ'=0.1 as above, the deviation in large signaltransconductance is now an increase of only 0.25%.

Other goals were a low common-mode output current resulting from adifferential input and a low sensitivity of differential-modetransconductance to any common-mode signal voltage. The common-modeoutput current caused by differential inputs+ΔVgs/2 and -ΔVgs/2 is##EQU6##

For the example of θ'=0.1 and ΔVgs of 1V this is G/40. The resultingoutput common-mode voltage will be an even smaller fraction of theoutput differential-mode voltage if the common mode output impedance isdesigned to be smaller than the differentialmode output impedance, as inthe integrated CMOS designs presented below.

The variation in differential-mode conductance G for any residualcommon-mode signal or from any common-mode voltage offset due totransistor mismatching, ΔVgso may be obtained by substituting for Go ineqn (13) from eqn (6) and differentiating to give ##EQU7##

So even for a common-mode offset as large as 25 mV (=1V/40), thelarge-signal transconductance will be modulated by only 2.0/40=0.5%.

For best performance the transistors should be well-matched in geometryand electrical parameters, but the invention is tolerant of small devicemismatches.

The output conductance of the above circuit is equal to the drain-sourceconductance of the transistors, typically of the same order as thetransconductance. To prevent appreciable modulation of Vds by the outputcurrent variations, which would modulate the transconductance andintroduce non-linearity, the transistor drains need to drive into alow-impedance load. Also, in general, for a transconductance amplifierto be useful in circuit applications, its output impedance needs to beat least an order of magnitude greater than the transconductance. Thusan output buffer transresistance stage needs to be added to the pair oftransistors to realise a useful circuit element.

In principle, as shown in the half-circuits of FIGS. 3 and 4, a simplecommon-gate MOS stage 31 (FIG. 3) or common-base bipolar stage 32 (FIG.4) could be used. However such a stage has a maximum input conductanceof the order of I/(kT/q) and has limited output impedance.

FIG. 5 shows a transconductor half-circuit using a preferred outputstage, which operates as follows.

In the quiescent state, the current through voltage-controlled currentsource 54 and transistor 57 is Ix, the current through current source 56and transistor 51 is Iz, the current through current source 55 andtransistor 32 is Iy, and the current through the input transistor 10 isIz+Iy. The voltage control terminal 33 is set such that the drain-sourcevoltage between node 52 and ground 53 is low enough to bias transistor10 in its linear, or triode, region. The input signal voltage, IP+, tothis half-circuit is superimposed on the gate voltage of transistor 10.A positive incremental input signal voltage will cause an increase indrain current in transistor 10 and will tend to cause the voltage ofnode 52 to decrease. This will increase the collector current oftransistor 32 and cause a larger drop in the base voltage of transistor51. In conjunction with transistor 57, this causes an increase incurrent through transistor 51, which will steer the incremental currentaway from transistor 32. An equal but opposite incremental current willflow through transistor 57, causing the signal current originallyinduced in transistor 10 to appear at the output terminal 58.

In this way, the input impedance seen by the drain of transistor 10 isreduced below that of common-base transistor 32 by a factor equal to theloop gain of transistors 32 and 51, so that node 52 is maintained at aconstant voltage for a wide range of input voltages. The outputimpedance is also increased over that of transistor 32 by thefolded-cascode action of transistor 57.

The full transconductor would include two such half-circuits, driven bya pair of complementary input signals IP+ and IP-. From the aboveanalysis this fully-differential transconductor element would have alinear transfer function and a high output impedance, as desired.

FIG. 6a shows a symbolised transconductor 69 having complementarydifferential inputs 610 and 611 and differential outputs 63 and 64.Optional additional complementary inputs are indicated by terminals 612and 613. The purpose of these inputs is explained later with referenceto FIG. 22.

FIG. 6b shows the circuit diagram of a transconductor designed andconstructed using discrete components. The components used were standardparts as illustrated, except for the MOS transistors, which were testdevices from a 2.5 μm CMOS process.

The circuit includes two half-circuits similar to FIG. 5, but with thecurrent sources 54 and 56 implemented using MOS transistors 61 in onehalf-circuit and 62 in the other. Extra circuitry is included tostabilise the common-mode output voltage and to reduce the common-modeoutput impedance as follows. The output terminals 63 and 64 areconnected to the gates of MOS transistors 65 and 66 which are biased inthe triode region by bias voltage VB applied to the base of bipolartransistor 67. This causes a current through the collector of transistor67. To first order, this current is independent of the outputdifferential voltage appearing between terminals 63 and 64 but increaseslinearly with the common-mode voltage of these terminals. This currentis transmitted to the CM bias stage 68, which is shown in more detail inFIG. 7. The current from the collector of transistor 67 (FIG. 6b)appears at terminal 71 where it passes through a current mirrorcomprising transistors 72, 73 and emitter degeneration resistors 74, 75.The difference between this current and the current set by the bias ofcurrent source 76 passes through a drain-gate connected MOST 77. Theresulting voltage appearing at terminal 78 is used to drive the gates ofsimilar MOSTs 61, 62 (FIG. 6b), which are matched devices and so willgive equal currents. In this way, any increase in common-mode outputvoltage at nodes 63, 64 causes an increase in collector current intransistors 67, 72 and 73, which in turn results in a decrease incurrent in MOSTs 77, 61 and 62, which will act to restore thecommon-mode voltage at terminals 63, 64 without changing anydifferential-mode output voltage. The value of this common-mode outputvoltage is adjustable by means of the current source 76.

Various circuits have been built and investigated using suchtransconductors. The simple circuit of FIG. 8 comprises an inputtranscondutor 81 acting as a voltage-controlled current source feedinginto a second transconductor 82 with inputs and outputs connected tosimulate a resistive load. With the bias voltage (FIG. 6b) VB set at1.1V, a transconductance of 210 μA/V was obtained. The observed thirdharmonic distortion of the output signal is shown by curve 91 in FIG. 9,plotted against output signal level. With an output level of 1Vpeak-to-peak, output distortion is 73dB below the fundamental, andreduces by 12dB per 6dB drop in signal level.

An example of the use of such a transconductor is in active filters. Itis known that a gyrator can be realised using a pair ofvoltage-controlled current sources. FIG. 10 shows a pair oftransconductors 101 and 102 interconnected to act as adifferential-input differential-output gyrator. Starting from a standardLC ladder prototype such as shown in FIG. 11, known techniques are usedto replace the inductor(s) 111 by gyrators and grounded capacitors, togive the circuit of FIG. 12, where 123 and 124 are gyrators. Convertingthis circuit to a fully-differential equivalent and replacing thegyrators by pairs of transconductors, gives the circuit of FIG. 13.

The input transconductor 131, replacing the voltage-controlledcurrent-source 121, feeds into a second transconductor 132 with inputsand outputs interconnected to simulate the resistive load 122.Transconductors 133, 134 and 135, 136 replace the gyrators 123, 124 andtransconductor 137 with inputs and outputs interconnected simulates theoutput termination resistance 125.

Complete filters of this type have been constructed usingtransconductors of the type shown in FIG. 6a. FIG. 14 shows a 3rd order0.1dB Chebyshev ladder-based filter. In this circuit the capacitors 144are floating, connected across the differential inputs, in place of thepairs of grounded capacitors 138 in FIG. 13. This reduces the totalcapacitance by a factor of four. The stop-band and pass-band frequencyresponses of the circuit of FIG. 14 are shown in FIGS. 15a and 15brespectively. The harmonic distortion of the second harmonic (161) andthe third harmonic (162) varies with frequency, as shown in FIG. 16. Atthe worst-case frequency of 850 Hz, the peak of the third harmonicdistortion is increased for a given output level by the voltageamplification at the internal nodes and by the four transconductors 143each contributing to the distortion. Even so, only 63dB of thirdharmonic distortion is apparent at an output of 1V peak-to-peak. Notethat resistors 141, 142 were used for the terminations instead oftransconductors to reduce the complexity of this prototype filter. Theresults of FIG. 9 imply that the use of additional transconductors torealise these input and output terminations would not drastically affectthe distortion of this circuit.

Filters with transmission zeros such as elliptic filters can also berealised with simple circuit topologies using transconductors. Forexample adding a capacitor 181 to the all-pole LC ladder prototype ofFIG. 11 gives an LC ladder prototype as shown in FIG. 18 which realisesa transmission zero. As before, by replacing the inductor 182 by thegyrator-capacitor equivalent, converting to a fully-differentialtopology, and then replacing the gyrators by transconductor pairs, thisgives the circuit of FIG. 19, which is similar to FIG. 13 but containsextra capacitors 191, 192.

This circuit could be used to implement an integrated filter. However,capacitors fabricated in integrated circuit technology have associatedparasitic capacitances to ground, typically of the order of 10 percentof their inter-electrode capacitance and associated mainly with one ofthe two electrodes. If this value could be predicted, its effect on thefrequency response could be directly compensated by alteration of thenominal value of the grounded capacitors connected to the same node. Ingeneral, however, these parasitics are subject to uncorrelatedvariations with fabrication tolerances and vary with temperature andvoltage causing non-linearity and frequency response deviation anddrift.

FIG. 20 shows the circuit of FIG. 19 modified to reduce the effect ofthese parasitic capacitances. Capacitor 191, value Cx is replaced by thepair of equal capacitors 201, 202, value Cx and associated currentamplifiers 203, 204. These current amplifier stages have a low inputimpedance and so plates 205, 206 of capacitors 201, 202 connected to theamplifier inputs are effectively grounded, eliminating the effect of anyparasitics 215, 216 to ground on these plates. Also, the current flowingout of node 207 with voltage V1+ and into node 208 with voltage V3+through wires 209 and 210 respectively is equal to s.Cx.(V1+-V3+). Thisis exactly equal to the current flowing through the terminals ofcapacitor 191 in the circuit of FIG. 19. Similarly capacitor 192 of FIG.19 is replaced by an exact equivalent network comprising capacitors 211,212 and current amplifiers 213, 214.

These current amplifiers could be realised as simple commonbase stagessuch as shown in FIG. 21, in which an increase in current flowing intonode 211 will decrease the current through transistor 212 and thus givean equal increase in the current flowing out of node 213.

However, a simpler complete filter circuit results from incorporatingthis function in the transconductors as follows. Adding an extraterminal 221 to each transconductor half-circuit of FIG. 5 gives thecircuit of FIG. 22. Node 52 is a low-impedance point and any currentinjected into the terminal 221 will have the same effect as an increasein the current of the input MOST 10, appearing at the output terminal 58at a higher impedance and appropriate polarity. The function of thecurrent amplifiers can thus be incorporated in the transconductorcircuits with no extra active components.

FIG. 23 shows the all-pole prototype filter of FIG. 14 modified toinclude transmission zeros in the way just described, to implement a0.1dB Cauer filter. The filter has four transconductors 231-234 of whichtwo, 232 and 233, have extra terminals 235-238. Capacitors 239-2312 areconnected between respective inputs to transconductors 231, 234 and theopposed polarity extra terminals of transconductors 233, 232. Thecapacitors 239-2312 have the same capacitance value Cx. FIG. 24 showsthe observed frequency response. FIG. 25 shows the variation with inputsignal frequency of harmonic distortion at the second harmonic (251) andthird harmonic (252). The distortion performance is similar to thatobserved from the Chebyshev filter as shown in FIG. 16.

The prototype circuits described above used a combination of MOS andbipolar transistors. A fully-integrated design using only n-channel andp-channel MOSTs is possible. FIG. 26 shows the circuit diagram of such adesign. This circuit was designed for fabrication in a standard 2.5 μmCMOS process to operate from a single 5V±5% power supply 262 over arange of junction temperatures of from -25 to 80 deg C. and over atypical range of fabrication tolerances. The nominal transconductance is8.5 μA/V and typical power dissipation is 0.9 mW. Typical open-circuitvoltage gain is 940, input signal range 2.5 V±1.05 V, output signalrange 2.5 V±0.9 V.

Most nodes in the complete transconductor filter circuits describedabove are driven from two transconductor outputs. Rather than using twocomplete and separate transconductors, however, the signal currents fromthe input MOSTs may be added by connecting both their drains to the samelow-impedance node and sharing the output buffer stage, to give thesingle dual-input transconductor 261. This reduces the component countand gives a higher output impedance.

The fully-integrated design of FIG. 26 is such a circuit, withdifferential input signals applied between terminals 2614 and 2616 andbetween terminals 2613 and 2617. MOSTs 268, 267 and 2615 serve the samefunction as transistors 32, 51 and 57 respectively of the transconductorhalf-circuit of FIG. 5, as follows. MOST 267 keeps the current throughMOST 268 constant and so keeps node 269 at a constant voltage controlledby VB (2610). This drain-source voltage across MOSTs 2611 and 2612 issmall enough to keep them in the linear, or triode, region of operationas desired to give a linear transconductance. The total signal currentis applied from the MOSTs 2611 and 2612 through folded-cascode MOST 2615to the output 265. Similarly, inverse signals at terminals 2616 and 2617are applied to the gates of MOSTs 2618 and 2619 and cause an inversesignal current through MOST 2620.

The common-mode feedback to stabilise the output common-mode voltagediffers from that of the prototype transconductor of FIG. 6. The outputvoltages 265 and 266 are connected to the gates of the parallel triodes263 and 264 to give a common-mode signal current independent of outputdifferential voltage as before. This current is now reflected andamplified through current mirror 2626, 2627 and is reproduced equally bydevices 2630 and 2629, controlled by device 2628, buffered from theoutput by common-gate MOSTs 2621 and 2622 respectively. The value of thecommon-mode output voltage is set indirectly by input bias voltageapplied to terminal 2671, which sets the value of the current sources2635, through transistors 2636, 2637.

For application in the filter circuits described above it is importantto minimise the phase delay between the input voltage and the outputcurrent. Such phase delay will cause the phase delay between the inputvoltage and output voltage to exceed the 90 degrees expected, whendriving a capacitive load to implement an integrator stage. Such "excessphase" can cause large peaking of the filter frequency response near thepass-band edge and is a well-known phenomenon in more conventionalactive filters.

To minimise this excess phase, capacitors 2631, 2632, 2633, 2634 havebeen included. These are connected between the drain terminals 269, 269,2634, 2634 respectively and the inverse input terminals 2617, 2616,2614, 2613 respectively. FIG. 26A illustrates the principal of operationof these componants. Each pair of capacitors C is connected betweenrespective gate terminals of a pair of input transistors T₁ and T₂. Inthis way a component of signal current which leads the drain current ofthe input MOSTs is added to the drain current to give the outputcurrent. The sizes of these capacitors are chosen such that this leadingsignal current cancels the lagging component of the input transistordrain current. This technique is similar to the well-known technique ofneutralisation used in the design of high-speed bipolar differentialamplifier stages. In practice, the capacitors are made larger, so as toalso compensate for phase delay through the output stage. For thisparticular design, the output stage contributes about as much phasedelay as the input MOSTs, so the capacitors were double the originallychosen size.

After adjusting the capacitor values to give zero phase lag for nominalparameters at room temperature, the maximum simulated phase deviationover variations of process parameters and temperature is only 0.001degrees/kHz. This excellent phase stability is due partly to the lowtemperature coefficients of the capacitors and partly to thestabilisation of the transistors conductances.

FIG. 27 shows the simulated output harmonic distortion of thistransconductor design, plotted against input signal amplitude.

For the complete filter, two variants of this transconductor arenecessary. FIG. 28 shows a transconductor 280, identical to the FIG. 26arrangement but with additional inputs 281-284 to the input transistordrains connected to nodes 285 and 286 to facicitate the implementationof transmission zeros as described above. These connections are bufferedthrough transistors 287-2810 biased in triode region to act as resistorsas shown. This is necessary to buffer the nodes 285, 286 from the loadcapacitance to prevent degradation of the stability of the 2811/2812 and2813/2814 feedback loops.

The second variant 291 is shown in FIG. 29 and is again similar to thetransconductor 261 shown in FIG. 26 except:

a. MOSTs 295/296 and 297/298 are tied together;

b. there is no phase neutralisation, hence capacitors 2631, 2632, 2633,2634 are omitted; and

c. the common-mode stabilisation circuitry is omitted and replaced by adifferential-to-single-sided convertor 299 giving a single output 292.

This transconductor variant 291 is used in the control loop shown inFIG. 30 to stabilise the transconductance of itself and of all the othersimilar transconductor in the filter against process and temperaturevariations. Since all the transconductors in an integrated filter willbe fabricated on the same chip and in close proximity, the tracking ofprocess parameters and temperature will be close, so thetransconductances will also track closely.

A voltage VR is applied to 2910 of a transconductor 291. A voltage VR/8from the resistive potential divider 301 is applied across the inputs2910, 2911 of a transconductor 291 (FIG. 29). The current from thetransconductor 291 is driven through an offchip resistor 304. Thevoltage developed at the end 305 of this resistor is compared with VR atthe pad 306 by an error amplifier 307 which drives the bias voltage VBat pad 308 connected to the input 294 to the transconductor 291,modulating its transconductance and thus closing the feedback loop.

The error amplifier 307 was realised in this case as a simplesingle-stage folded cascode load-stabilised operational transconductanceamplifier using n-channel and p-channel MOSTs (not shown).

The simulated phase margin of this loop remains greater than 82 degreesover anticipated process and temperature variations. The circuitexhibits a simulated offset of 1.5 percent in the transconductance ofthe slave transconductance cells compared to the reference resistance.This is caused primarily by the single-ended input to the transconductor291 giving a fall-off in its transconductance, even with the attenuatedinput voltage of only about 0.3 V. This offset (being stable to 0.1%with temperature,) could be trimmed out by alteration of the referenceresistance 304. Random offset voltages of the error amplifier 307 andtransconductor 291 will give errors of 0.04%/mV and 0.3%/mVrespectively.

The circuit diagram of a complete 5th order elliptic filter based on adoubly terminated LC ladder filter is shown in FIG. 31. This occupies atotal chip area of 5.3 mm2 of which the transconductors and capacitorsoccupy only 2.5 mm2. The simulated typical power dissipation is 15.7 mWincluding 9.0 mW of the two output voltage-follower op amps 311 and 312.The operational amplifiers 311 and 312 are needed to buffer thehigh-impedance filter output to drive low-impedance off-chip loads andare also realised by MOST devices (not shown).

In contrast to switched-capacitor circuits, the entire filter canreadily be simulated using a standard circuit simulator such as SPICE,including the effect of all parasitics. Simulated frequency response isshown in FIG. 32, with (321) and without (322) phase neutralisation. Thephase neutralisation can be seen to make 0.2dB difference (323) in thepassband peaking. Small errors in the neutralisation will thus have avery small effect on pass-band ripple. FIGS. 33 and 34 show the responsetoleranced over process and temperature extremes. Total simulated outputdifferential noise voltage integrated from 0 to 1.5 fF is typically 175μV, giving a 71.1dB dynamic range relative to a 1 v peak-to-peakdifferential output voltage swing.

An alternative circuit is shown in FIG. 35. In this circuit thetransmission zeros are realised by simple floating capacitors at theexpense of sensitivity to parasitic capacitance variation. For thisparticular filter response these floating capacitors are relativelysmall, so the parasitics should only have a minor effect. Also the partof the load capacitance driven by each transconductor is fully-floatingbetween the output terminals to reduce the total capacitance. Somegrounded capacitance is necessary for common-mode stability. The area ofthis filter is 4.0 mm², of which the capacitors and transconductorsoccupy only 2.0 mm², the remaining space being occupied by the outputbuffer op amps and interconnect to bonding pads.

A prototype 5th order 0.18 dB Cauer CMOS low pass active integratedfilter circuit corresponding to the circuit shown in FIG. 35 has beenproduced.

All transconductors have the same tansconductance and are identical forgood matching. Thus the shape of the frequency response is set by theratios of the capacitors, which can be set accurately and reproduciblyby suitable layout techniques. Sensitivity to residual manufacturingvariations is low, since the node capacitances correspond to L and Cvalues of the prototype LC ladder.

Stray capacitance to ground from the top plates of the groundedcapacitors arise from the input and output capacitances of thetransconductors, from capacitance from the interconnecting metallisationto the substrate, and from capacitances from the top and bottom platesof floating capacitors to ground. These parasitics appear directly inparallel with the intended plate-to-plate capacitance, and have to becalculated and compensated for by adjustment of the capacitor values toobtain the desired frequency response. However, such strays aretypically only a few percent of the total effective capacitance on eachnode, so a small error in this correction will have minimal effect onthe response of the filter. This contrasts with the case ofswitched-capacitor filters, where the input switched capacitors areusually smaller than the switch and amplifier input capacitancesdemanding the adoption of "parasitic-insensitive" techniques.

The load capacitance on each transconductor output is implemented by acombination of floating and grounded capacitances. The use offully-floating capacitors can reduce the total capacitor area for agiven circuit impedance by a factor of four. However, to ensurehighfrequency common-mode stability, some grounded capacitance isnecessary. In this design, the total capacitor area was halved comparedto a fully-grounded design.

FIGS. 36 to 39 summarise results obtained from the first tested device.The response at the nominal 28 kHz cut-off frequency shown in FIGS. 36and 37 agrees closely with the theoretical 0.18 dB passband ripple and61.4 dB stopband attenuation.

Simply by adjusting the control voltage VB (through changing Rref), the3 dB cut-off frequency can be varied from 5 to 90 kHz before beinglimited by quiescent bias constraints. In the high frequency extremethere is about 0.2 dB extra peaking at the passband edge, at thelow-frequency extreme the first passband minimum is accentuated 0.1 dB.The small size of these deviations demonstrates the effectiveness of thephase neutralisation in reducing excess phase effects.

FIG. 38 shows a plot of relative second and third harmonic distortioncomponents against output signal amplitude at the worst-case frequency(10 kHz) for a 28 kHz filter. At low signal levels the distortion isdominated by the second harmonic, presently thought to be due to bothdevice mismatches and test-board imperfections. The third harmonicincreases at the expected rate of 12 dB/octave, being 64 dB down at anoutput level of 2V peak-peak (-3 dBV).

FIG. 39 shows the spectral dependence of the output noise. This isdominated by the 1/f noise of the n-channel devices and peaks near thepassband edge. The total noise integrated over the passband is 0.34mVrms, which gives a dynamic range of 69.4 dB with respect to 1 Vrms.

Compared to switched-capacitor filters, continuoustime filters accordingto the invention have the following advantages:

(i) No aliasing of input or imaging of output signals: This simplifiesthe interface to unsampled systems, by removing the need foranti-aliasing prefilters and smoothing post-filters; sampled-datasystems can include c-t filter blocks without clock-synchronisationproblems.

(ii) No aliasing of high-frequency power supply or amplifier noise: InSC filters, the op amp PSRR reduces with frequency allowinghigh-frequency components of power supply ripple (e.g. from switchingregulators) to be aliased down to baseband with little attenuation.Similarly the h.f. noise from wideband op amp output stages is aliaseddown to baseband. Such effects are particularly significant in theelectrically noisy environment of combined analogue-digital chips.

(iii) Circuit simplicity: SC filters require the generation ofmulti-phase complementary clock waveforms and their distribution toswitches. This complicates the interconnect net, and constrains layout.

(iv) Simplicity of circuit synthesis: Conventional active filter methodscan be used to obtain component values, rather than the complex sampleddata algorithms required for accurate design of SC filters.

(v) Computer simulation: The complete circuit can be simulated usingSPICE down to the transistor level, to include the effects of allparasitics. Together with automated circuit extraction programmes, thisallows a full CAD loop to be established between the circuit laid outand the desired performance specification. This is impossible with SCfilters, even using special purpose simulators and with manualintervention to incorporate foreseen second order effects. This isperhaps the most significant advantage for custom integrated filters,where the risk of first-pass design malfunction and consequent redesigninteractions must be minimised to provide an economic and crediblecustomer interface.

A major disadvantage of c-t filters is the requirement for an on-chipcontrol loop however, this is not a significant overhead for complexfilters.

The above analysis has concentrated on a circuit using n-channel MOStransistors. The results are also applicable to circuits using othersimilar devices such as p-channel MOSTs, junction field-effecttransistors or thermionic valves. The exact form of equations 1 and 2 isunimportant: any pair of devices of a type with an approximately linearrelationship between the current out of one terminal and the voltageapplied between two other terminals could be used as input devices insimilar circuits in a similar mode and improved linearity obtained overa simple singlesided circuit. For example, MOSTs with sub-micron channellengths may exhibit an almost linear rather than square-law dependenceof drain current on gate-source voltage, even in saturation-modeoperation and could be especially suitable for high-speed filters.

The above transconductor circuits are single-input and dual-inputtransconductors. The circuits can be generalised by including more inputdevices in parallel to realise multi-input transconductors. The inputdevices can be scaled in geometry to provide weighted inputs.

The above description has concentrated on the application oftransconductor circuits to active filters. The transconductor can alsobe used in other known applications of voltage-controlled currentsources, such as voltage-to-current converters, waveform generation,voltage-controlled oscillators and integrators. Signals can be weightedand summed by using transconductors connected in parallel with commonoutput terminals or by using multi-input transconductors.

By modulating the drain voltage of the input transistors through thebias voltage VB, the output current becomes proportional to both thedrain voltage and to the input differential signal voltage. In this waya two-quadrant multiplier is realisable. This could be used to mixsignals of different frequencies, possibly embedded in a filterstructure.

Alternatively, by keeping VB fixed at an appropriate voltage, thetransconductance obtained becomes a function of temperature and thecircuit could be used as a temperature transducer. If the transconductoris part of an oscillator, this would become a temperature-controlledoscillator. Comparing its oscillation frequency against a referencefrequency would give a digital output.

The transconductance of the input devices will be affected by strain inthe substrate. If two or more transconductors are fabricated inproximity on the same substrate but in different orientations and drivenwith equal bias voltages, the ratio of their transconductances is ameasure of the local strain. This ratio could be measured by extracircuitry. For example, the oscillation frequencies of two orthogonaltransconductor oscillators could be obtained by digital countercircuitry.

Even within the field of application of active filters, other types ofactive filter than the LC ladder based designs shown above are possible.For example, biquadratic stages of signal-flow-graph networks can beused. Also the capacitor network around the transconductors need not bepermanently connnected, but could include different capacitors, whichcould be taken in or out of the network by means of series or shuntswitches, such as CMOS transmission gates. These switches could becontrolled by electrical control signals applied externally to thefilter circuit, or by on-chip fusible links or EPROM devices. Thenetwork could also be laid out to enable permanent reconfiguration ortrimming of the network by electron-beam or laser technology.

Also, the capacitor network can be switched to make it timevarying, toincorporate functions such as signal frequency shifting orchopper-stabilisation.

The phase neutralisation technique described above is applicable toactive filters using other differential input amplifier stages.

The common-mode feedback techniques described above are also applicableto other designs of differential-output amplifiers, such as high-gainoperational transconductance amplifiers.

I claim:
 1. A differential input transconductor including a pair offield-effect transistors each having a substrate terminal, a sourceterminal, a gate terminal and a drain terminal, wherein the sourceterminals of the pair are connected together to a first fixed voltage;the substrate terminals of the pair are connected to a second fixedvoltage; means is provided to set equal quiescent voltages on the gateterminals and to superimpose equal but opposite signal voltages on thetwo gate terminals; and means is provided to maintain the voltages onthe drain terminals of the two transistors at an equal voltage chosen tokeep the transistors in the triode region of operation for the expectedvariation of the gate-source voltage, the drain terminals of the pair oftransistors being connected to an output circuit to maintain the voltageon the drain terminals at the chosen voltage and to transmit adifferential mode output current component of the transconductor viaoutput terminals to a load circuit at a higher impedance level, theoutput circuit comprising a first pair of transistors each defining acommon-gate MOS stage and the output circuit including a further pair oftransistors each of which is connected to a respective one of the firstpair of transistors of the MOS stage, said first pair and said furtherpair being of opposite polarity type and being connected together in afeedback loop such that the input impedance seen at the drain terminalsof the pair of field effect transistors is reduced below that of thecommon-gate MOS stage by a factor equal to the loop gain of the feedbackloop.
 2. A differential input transconductor including a pair offield-effect transistors each having a substrate terminal, a sourceterminal, a gate terminal and a drain terminal, wherein the sourceterminals of the pair are connected together to a first fixed voltage;the substrate terminals of the pair are connected to a second fixedvoltage; means is provided to set equal quiescent voltages on the gateterminals and to superimpose equal but opposite signal voltages on thetwo gate terminals; and means is provided to maintain the voltages onthe drain terminals of the two transistors at an equal voltage chosen tokeep the transistors in the triode region of operation for the expectedvariation of the gate-source voltage, a pair of capacitors beingconnected between respective drain terminals of each transistor and thegate terminal of the opposite transistor, to minimize the phase delaybetween the input voltage and the output current of the transconductor.3. A differential input transconductor including a pair of field-effecttransistors each having a substrate terminal, a source terminal, a gateterminal and a drain terminal, wherein the source terminals of the pairare connected together to a first fixed voltage; the substrate terminalsof the pair are connected to a second fixed voltage; means is providedto set equal quiescent voltages on the gate terminals and to superimposeequal but opposite signal voltages on the two gate terminals; and meansis provided to maintain the voltages on the drain terminals of the twotransistors at an equal voltage chosen to keep the transistors in thetriode region of operation for the expected variation of the gate-sourcevoltage, the drain terminals of the pair of transistors being connectedto an output circuit to maintain the voltage on the drain terminals atthe chosen voltage and to transmit a differential mode output currentcomponent of the transconductor via output terminals to a load circuitat a higher impedance level, the voltages at the output terminals beingapplied to the inputs of a summing amplifier stage to give an outputsignal representing the common-mode component of the output terminalvoltages, and this output signal controlling a pair of current sourcesinjecting equal currents into respective nodes of two symmetric halvesof the transconductor, the polarity of these currents being such as tostabilize the common-mode component of the output voltages.
 4. Adifferential input transconductor including a pair of field-effecttransistors each having a substrate terminal, a source terminal, a gateterminal and a drain terminal, wherein the source terminals of the pairare connected together to a first fixed voltage; the substrate terminalsof the pair are connected to a second fixed voltage; means is providedto set equal quiescent voltages on the gate terminals and to superimposeequal but opposite signal voltages on the two gate terminals; the drainterminal of each one of the pair of field-effect transistors isconnected to a respective emitter of a first pair of bipolartransistors; means is provided to maintain the base terminals of thebipolar transistor of the first pair of bipolar transistors at aconstant voltage chosen so that the field-effect transistors remainbiased in the triode region of operation over the expected variation ingate-source voltage; the collector terminal of each of the bipolartransistors of the first pair of bipolar transistors is connected to arespective one of a first pair of current sources and to the baseterminal of the respective one of a second pair of bipolar transistors,the second pair of bipolar transistors being of opposite polarity typeto the first pair of bipolar transistors; the collector of each saidrespective second pair of bipolar transistors being connected to theemitter of the said respective bipolar transistor of the first pair ofbipolar transistors; the emitter of each of said second pair of bipolartransistors being connected to the emitter of a respective one of athird pair of transistors having respective collector terminals and alsoto the respective one of a second pair of current sources; outputcurrents being taken from each of the collectors of the third pair oftransistors, via a respective output terminal.